The design of a pulse counter to 16 channels pulse with EDA technology of CPLD+VHDL is presented in the paper.
介绍了用CPLD+HDL的EDA技术作为开发手段,实现对16通道脉冲信号计数的脉冲计数器的设计。
Combining advantages of CPLD and SCM,the article introduces a design and realization of pulse counter which bases on single-chip microcomputer of STC89LE52 and CPLD.
脉冲计数器是数字电路中的一个典型应用,论文综合CPLD与单片机各自的优势,介绍了一种CPLD+STC89LE52脉冲计数器的设计方案并加以实现。
impulse register
脉冲寄存器脉冲计数器
counter ,electronic impulse (scalers)
电子脉冲计数器（定标器）
automatic microwave pulse counter
自动微波脉冲计数器
Kind of Multi-channel Pulse Counter Design Based on EDA
一种多通道脉冲计数器的EDA方法设计
adjustable impulse counter with automatic rerun
自动重复运行可调脉冲计数器
Design of Pulse Counter Based on CPLD and SCM
基于CPLD和单片机的脉冲计数器设计与实现
Pulse counter with manual reset and pneumatic output signal.
有手动复位和气压输出信号的脉冲计数器。
Pulse counter with manual reset and electric output signal.
有手动复位和电气输出信号的脉冲计数器。
A serial counter is also called a ripple counter.
串行计数器亦叫脉冲型计数器。
A 3 bit counter can be used to count up to seven pulses.
三位计数器就可用来累计7个脉冲。
The background count of the detector is 4～6 counts 1 min.
探测器的本底计数率为4―6脉冲1分。
Design New Parametric Pulse Generator on FPGA;
新型参数化脉冲发生器的FPGA设计
Use of Gate of Arithmometer in Measuring Width of Impulse;
巧用定时计数器门控位测量脉冲宽度
The Design of"Plus"/"Minus"Pulse DCO Based on Verilog
基于Verilog的“加”、“扣”脉冲式数控振荡器设计
Those of the other pulse should be subtracted to the content of the counter.
另一列脉冲则应从计数器中的数中减去。
Design of Digital System of Multi-Channel Pulse Amplitude Analyzer Based on ARM-Linux
基于ARM-Linux的多道脉冲幅度分析器数字系统设计
The Design of Multi-channel Analyzer Based on DSP
基于DSP的数字多道脉冲幅度分析器设计
Capacitance calculation and simulation of Blumlein pulse modulator
Blumlein型脉冲调制器电容等参数的模拟与计算研究