We can selectively save some compressed data on CPU cache and main memory.
我们可以在主存和cache中选择性地存储一些压缩了的数据,这样就变相地增加主存与cache的存储容量,从而明显地降低失页率以及减少了访问虚拟存储器的次数和时间消耗;同样地在一定情况下主存与cache之间可以直接传送压缩的数据来进行数据交换,这样缩短了数据传输的时间,达到了提高整个系统运行效率的目的。
There are some research on the optimization techniques which can improve the speedup of multimedia applications for the shared memory 2D SIMD architecture.
共享主存二维SIMD结构已经广泛应用于多媒体处理加速部件,其数据并行性可以大大提高处理器的运算能力。
In this dissertation, wefocus on the shared memory supercomputers which are suffering from an inherentfragility, .
本文所探讨的超级计算机系统由于共享主存的原因，对故障具有先天的脆弱性，任何一个硬件或者软件的故障都可能会造成整个系统的失效。
This article introduced a way of interface design of main memory for Cache experiment on a traditional experiment packet of computer organization and architecture.
本文介绍了一种在传统计算机组成原理实验仪上,开设Cache实验时的主存储器的接口设计方法,并给出了电路和数据通路分析,最后进行了性能比较。
Embarking from the development and application characteristics of DRAMs,aiming at the problems about main memory space and the addressing,parallel main memory structure by using multi-bank overlap access,and dynamic refurbish and so on which are needed to be solved when parallel main memory structure is constituted by using DRAMs.
从DRAM的发展及应用特点出发,针对使用DRAM构成计算机主存时应解决的主存空间及寻址、多体交叉访问构成并行主存结构、动态刷新等问题,以采用DRAM控制器W4006AF构成80386微机主存的设计为例,对主存的构成及工作原理进行了详细分析,对于分析和设计计算机主存具有很好的参考价值。