A design of 32-bit floating-point multipliers by using a structure of modified 4-2 column compression;
基于改进4-2压缩结构的32位浮点乘法器设计
Floating-Point Multiply-Accumulative Processing Element on FPGAs;
浮点乘累加处理单元的FPGA实现
The Realization of the floating-point Algorithm for square root Based on fixed-point DSP;
基于定点DSP的浮点开平方算法的实现
These styles are 64bits double precision floating point data,32bits single precision floating point data,32bits integer data and 16bits fixed point data.
为了实现不同数制的乘法共享硬件资源,提出了一种可以实现基于IEEE754标准的64位双精度浮点与32位单精度浮点、32位整数和16位定点的多功能阵列乘法器的设计方法。
5 μm CMOS technology and can perform a32 - bit floating point multiplication ( based on the proposed IEEE P75 4standard format) and a 32 - bit fixed point multipl.
5μm CMOS工艺实现 ,完成一次定点与浮点乘法操作的时间分别是 5 6 ns和 76 n