TCA Twin C Cache Architecture

基本解释双缓存架构〖3D加速芯片〗

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1)TCA Twin C Cache Architecture,双缓存架构〖3D加速芯片〗2)BDME (Bi C directional DME),双向直接内存执行〖3D加速芯片〗3)chip register architecture,芯片缓存器结构4)QPA Quad Port Acceleration,四端口加速结构〖芯片组〗5)cod(cache on die),芯片内集成缓存6)TCA Twin Cache Architecture,双缓存结构

最新行业英语

NC-C Network Computer C Client
implementation conformance statement (ICS)
External Observation
Business to government(B2G)
GRP Group Reference Pilot
UNC Universal Naming Convention
FACP Fully Automated Computer Program
pixel aspect ratio
clock unit
Line Repeater LR
TADIC Telemetry Analogue Digital Information Converter
textBox
normal magnetization
VAD Voice C Activated Dialing
RDR Real time Data Relay
USRT Universal Synchronous Receiver / Transmitter
straight line coding
TBP Three C Beam Projector
implement
complementing flip flop
NUI Network User Interface
private code
help menu
write head
n-chaiinel charge-coupled devicen
primary processingunit
System Application Architecture (SAA)
Radio Frequency Identification
character modifIel
FDC Fluid Digital Computer
code,data conversion
.qdi
IL (Intermediate Language)
afterglow screen
information encapsulation
system manager

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